Melikyan, V. Sh.Durgaryan, A. A.Petrosyan, H. P.Stepanyan, A. G.2023-10-052023-10-052011Power Efficient, Low Noise 2-5 GHz Phase Locked Loop / Melikyan V. Sh., Durgaryan A. A., Petrosyan H. P., Stepanyan A. G. // Электроника и связь : научно-технический журнал. Тематический выпуск «Электроника и нанотехнологии». – 2011. – №4(63). – С. 66-72. – Бібліогр.: 8 назв.https://ela.kpi.ua/handle/123456789/60952A power and noise efficient solution for phase locked loop (PLL) is presented. A lock detector is implemented to deactivate the PLL components, except the voltage controlled oscil ator (VCO), in the locked state. Signals deactivating/activating the PLL are discussed on system level. The introduced technique significantly saves power and decreases PLL output jitter. As a result whole PLL power consumption and output noise decreased about 35-38% in expense of approximately 17% area overhead.enсистема фазового автопідстроювання частотизниження енергоспоживаннятремтіння частотистатичний струмдинамічний струмArticlePp. 66-72https://doi.org/10.20535/2312-1807.2011.16.4.244797621.3.049.771