2011

Постійне посилання на фонд

https://ela.kpi.ua/handle/123456789/36853

Переглянути

Перегляд 2011 за Автор "Durgaryan, A. A."

Зараз показуємо 1 - 2 з 2
  • Ескіз
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    Method of Parametrical Optimization of Multi-Core Processors
    (НТУУ «КПІ», 2011) Melikyan, V. Sh.; Poghosyan, A. M.; Durgaryan, A. A.; Petrosyan, H. P.; Simonyan, M. M.
    A post-layout design power optimization algorithm is suggested. Both, gate sizing and multi threshold optimization methods are implemented. The main advantages are the improved performance characteristics and intactness of the initial design placement and routing. Free layout spaces due to decrease of optimized cell sizes is suggested to be filled with decoupling capacitors which decreases power supply noises. The algorithm ensures decrease of static and dynamic power by respectably 19% and 11% for eight-core OpenSPARC processor architectures. It demonstrates improved optimization time compared to existing algorithms by about 29%, in expense of decrease of optimized power by 2-5%.
  • Ескіз
    ДокументВідкритий доступ
    Power Efficient, Low Noise 2-5 GHz Phase Locked Loop
    (НТУУ «КПІ», 2011) Melikyan, V. Sh.; Durgaryan, A. A.; Petrosyan, H. P.; Stepanyan, A. G.
    A power and noise efficient solution for phase locked loop (PLL) is presented. A lock detector is implemented to deactivate the PLL components, except the voltage controlled oscil ator (VCO), in the locked state. Signals deactivating/activating the PLL are discussed on system level. The introduced technique significantly saves power and decreases PLL output jitter. As a result whole PLL power consumption and output noise decreased about 35-38% in expense of approximately 17% area overhead.