(НТУУ «КПІ», 2011) Melikyan, V. Sh.; Poghosyan, A. M.; Durgaryan, A. A.; Petrosyan, H. P.; Simonyan, M. M.
A post-layout design power optimization algorithm is suggested. Both, gate sizing and multi threshold optimization methods are implemented. The main advantages are the improved performance characteristics and intactness of the initial design placement and routing. Free layout spaces due to decrease of optimized cell sizes is suggested to be filled with decoupling capacitors which decreases power supply noises. The algorithm ensures decrease of static and dynamic power by respectably 19% and 11% for eight-core OpenSPARC processor architectures. It demonstrates improved optimization time compared to existing algorithms by about 29%, in expense of decrease of optimized power by 2-5%.