Перегляд за Автор "Serhiienko, Pavlo"

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    Design of data buffers in field programmablr gate arrays
    (National Technical University of Ukraine "Igor Sikorsky Kyiv Polytechnic Institute", 2022) Sergiyenko, Anatoliy; Serhiienko, Pavlo; Mozghovyi, Ivan; Molchanova, Anastasiia
    The design of the data buffers for the field programable gate array (FPGA) projects is considered. A new method of buffer design is proposed, which is based on the representation of the synchronous dataflow graph in the three-dimensional space, optimization of them, and description in VHDL. The method gives the optimized buffers which are based either on RAM or on the register pipeline. The derived pipeline buffer can be mapped into the shift register primitive of FPGA. The method is built in the experimental SDFCAD framework intended for the pipelined datapath synthesis.
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    Local feature extraction in images
    (National Technical University of Ukraine "Igor Sikorsky Kyiv Polytechnic Institute", 2021) Sergiyenko, Anatoliy; Serhiienko, Pavlo; Orlova, Mariia
    The methods of the local feature point extraction are analyzed. The analysis shows that the most effective detectors are based on the brightness gradient determination. They usually use the Harris angle detector, which is complex in calculations. The algorithm complexity minimization contradicts both the detector effectiveness and to the high dynamic range of the analyzed image. As a result, the high-speed methods could not recognize the feature points in the heavy luminance conditions. The modification of the high dynamic range (HDR) image compression algorithm based on the Retinex method is proposed. It contains an adaptive filter, which preserves the image edges. The filter is based on a set of feature detectors performing the Harris-Laplace transform which is much simpler than the Harris angle detector. A prototype of the HDR video camera is designed which provides sharp images. Its structure simplifies the design of the artificial intelligence engine, which is implemented in FPGA of medium or large size.