Design of data buffers in field programmablr gate arrays

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dc.contributor.authorSergiyenko, Anatoliy
dc.contributor.authorSerhiienko, Pavlo
dc.contributor.authorMozghovyi, Ivan
dc.contributor.authorMolchanova, Anastasiia
dc.date.accessioned2023-04-20T04:31:59Z
dc.date.available2023-04-20T04:31:59Z
dc.date.issued2022
dc.description.abstractThe design of the data buffers for the field programable gate array (FPGA) projects is considered. A new method of buffer design is proposed, which is based on the representation of the synchronous dataflow graph in the three-dimensional space, optimization of them, and description in VHDL. The method gives the optimized buffers which are based either on RAM or on the register pipeline. The derived pipeline buffer can be mapped into the shift register primitive of FPGA. The method is built in the experimental SDFCAD framework intended for the pipelined datapath synthesis.uk
dc.format.pagerangePp. 4-16uk
dc.identifier.citationDesign of data buffers in field programmablr gate arrays / Sergiyenko Anatoliy, Serhiienko Pavlo, Mozghovyi Ivan, Molchanova Anastasiia // Information, Computing and Intelligent systems. – 2022. – No. 3. – Pp. 4–16. – Bibliogr.: 42 ref.uk
dc.identifier.doihttps://doi.org/10.20535/2708-4930.3.2022.267302
dc.identifier.orcid0000-0001-5965-1789uk
dc.identifier.orcid0000-0003-3030-0074uk
dc.identifier.orcid0000-0001-5469-486Xuk
dc.identifier.orcid0000-0001-7328-7151uk
dc.identifier.urihttps://ela.kpi.ua/handle/123456789/54730
dc.language.isoenuk
dc.publisherNational Technical University of Ukraine "Igor Sikorsky Kyiv Polytechnic Institute"uk
dc.publisher.placeKyivuk
dc.relation.ispartofInformation, Computing and Intelligent systems, No. 3uk
dc.subjectFPGAuk
dc.subjectVHDLuk
dc.subjectsynchronous dataflowuk
dc.subjectdatapath synthesisuk
dc.subject.udc004.383uk
dc.titleDesign of data buffers in field programmablr gate arraysuk
dc.typeArticleuk

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Information, Computing and Intelligent systems, No. 3