(National Technical University of Ukraine "Igor Sikorsky Kyiv Polytechnic Institute", 2022) Sergiyenko, Anatoliy; Serhiienko, Pavlo; Mozghovyi, Ivan; Molchanova, Anastasiia
The design of the data buffers for the field programable gate array (FPGA) projects is considered. A new method of buffer design is proposed, which is based on the representation of the synchronous dataflow graph in the three-dimensional space, optimization of them, and description in VHDL. The method gives the optimized buffers which are based either on RAM or on the register pipeline. The derived pipeline buffer can be mapped into the shift register primitive of FPGA. The method is built in the experimental SDFCAD framework intended for the pipelined datapath synthesis.